1. Field of the Invention
The present invention relates to a gradation voltage selecting circuit, a driver circuit, a liquid crystal drive circuit and a liquid crystal display device. More particularly, the present invention relates to the gradation voltage selecting circuit, the driver circuit, the liquid crystal drive circuit and the liquid crystal display device which is used for a capacitive load exemplified in a liquid crystal panel.
2. Description of the Related Art
In recent years, Liquid crystal display devices have been used for a mobile electronic apparatus exemplified by a portable telephone. When the liquid crystal display devices are used for the mobile electronic apparatus, the liquid crystal display device is required to have a thin structure and a property of lower power consumption. Also, the liquid crystal display device is required to have the small circuit scale (chip size).
FIG. 1 is a block diagram showing the configuration of a liquid crystal display device of the related art. This liquid crystal display device is composed of a liquid crystal drive circuit provided on a chip, and a display portion 101 as a liquid crystal panel.
The liquid crystal drive circuit is composed of m-pieces gate driver circuits 102-1 to 102-m (m is an integer of 2 or more), n-pieces source driver circuits 103-1 to 103-n (n is an integer of 2 or more), and a power supply circuit 104.
The display portion 101 includes (m×n)-pieces pixels 110. Each of the (m×n)-pieces pixels 110 includes a pixel electrode 111, a counter electrode 112 opposed to the pixel electrode 111, and a thin film transistor (TFT) 113 of which the drain is connected to the pixel electrode 111.
The gate driver circuits 102-1 to 102-m are respectively connected to the display portion 101 through gate lines 105-1 to 105-m. The gate line 105-i (i=1, 2, - - - , m) is connected to the gates of the thin film transistors 113 of the n-pieces pixels 110 belonging to the i-th row among m rows. The first to the m-th gate control signal 107 in one horizontal period is supplied respectively to the gate driver circuits 102-1 to 102-m from the outside in this order. The gate driver circuit 102-i outputs a scanning voltage to the display portion 101 through the gate line 105-i in response to the gate control signal 107 from the outside.
The power supply circuit 104 includes a plurality of resistive elements connected in series. The power supply circuit 104 voltage-divides an external voltage and a ground voltage by using the plurality of resistive elements, and generates X-pieces (for example; X=9) different reference voltages. The X-pieces reference voltages are supplied to n-pieces source driver circuits 103-1 to 103-n. 
The source driver circuits 103-1 to 103-n are respectively connected to the display portion 101 through signal lines 106-1 to 106-n. The signal line 106-j (j-1, 2, - - - , n) is connected to the sources of the thin film transistors 113 of m-pieces pixels 110 belonging to the j-th column among the n columns. The X-pieces reference voltages are respectively supplied to the source driver circuits 103-1 to 103-n from the power supply circuit 104. A source control signal 108 and display data D1 to Dn are respectively supplied to the source driver circuits 103-1 to 103-n from the outside in one horizontal period. The display data D1 to Dn are digital gradation data. The source driver circuit 103-j outputs a gradation voltage in response to the display data Dj to the display portion 101 through the signal line 106-j based on the X-pieces reference voltages from the power supply circuit 104 and the source control signal 108 from the outside.
The thin film transistor 113 of the pixel 110 of the i-th row and the j-th column applies the gradation voltage between the pixel electrode 111 and the counter electrode 112 of the pixel 110, when the scanning voltage is applied to the gate line 105-i and the gradation voltage is applied to the signal line 106-j. 
FIG. 2 is a block diagram showing the configuration of the source driver circuit 103-j of the liquid crystal display device of the related art. The source driver circuit 103-j includes a shift register 121, a data register 122, a latch circuit 123, a level shifter 124, a gradation voltage selecting circuit 125 as a digital/analog (D/A) converter, a buffer amplifier 126 as an output circuit and a series resistance voltage dividing circuit 127. Herein, the above source control signal 108 supplied to the source driver circuit 103-j contains a shift pulse 128 and a transfer clock 129.
The shift register 121 shifts the shift pulse 128 successively synchronizing the shift pulse 128 supplied from the outside with the transfer clock 129. The data register 122 stores the display data Dj from the outside, and outputs the display data Dj to the latch circuit 123 synchronizing the display data Dj with the shift pulse 128 outputted from the shift register 121.
Here, the latch circuit 123 of the source driver circuits 103-1 to 103-m latches the output of the data register 102 of the source driver circuits 103-1 to 103-m with the same timing.
The level shifter 124 converts the level of the output of the latch circuit 123.
The series resistance voltage dividing circuit 127 includes a plurality of resistive elements connected in series. The series resistance voltage dividing circuit 127 voltage-divides the X-pieces reference voltages from the power supply circuit 104 by using the plurality of resistive elements, and generates Y different gradation voltages (Y>X).
The gradation voltage selecting circuit 125 generates Z-pieces output gradation voltages (Z>Y) based on the Y-pieces gradation voltages generated by the series resistance voltage dividing circuit 127, and the output (display data Dj) of the level shifter 124. The gradation voltage selecting circuit 125 selects the output gradation voltage in response to the display data Dj among the Z-pieces output gradation voltage. The buffer amplifier 126 outputs the output gradation voltage selected by the gradation voltage selecting circuit 125 to the signal line 106-j. 
FIG. 3 is a block diagram showing the configurations of the series resistance voltage dividing circuit 127 and gradation voltage selecting circuit 125 of the source driver circuit 103-j of the liquid crystal display device of the related art. The gradation voltage selecting circuit 125 is obtained by simplifying the gradation voltage selecting circuit described in Japanese Laid Open Patent Application H09-198012A (1997).
First, the series resistance voltage dividing circuit 127 will be explained.
Herein, above X is set to 9, and the X-pieces reference voltages are expressed as the reference voltages V0 to V8. The plurality of resistive elements of the series resistance voltage dividing circuit 127 are expressed as the resistive elements R0 to R15 connected in series.
Nodes T0 to T15 are respectively connected to one terminal of both terminals of the resistive elements R0 to R15. Nodes T1 to T16 are respectively connected to the other terminals of the resistive elements R0 to R15. The reference voltages V0 to V8 are respectively applied to even numbered nodes T0, T2, T4, T6, T8, T10, T12, T14 and T16 among the nodes T1 to T16.
Next, the gradation voltage selecting circuit 125 will be explained. The gradation voltage selecting circuit 125 includes a gradation voltage control portion 130, a first switching portion 131, a half gradation voltage generating portion 132 and a second switching portion 133.
Herein, the above Y is expressed as 17.
The first switching portion 131 contains Y-pieces switches S00 to S16 as an MOS transistor. The nodes T0 to T16 are respectively connected to the one ends of the switches S00 to S16. A node Ta is connected to the other ends of the switches S00, S02, S04, S06, S08, S10, S12, S14 and S16. A node Te is connected to the other ends of switches S01, S03, S05, S07, S09, S11, S13, and S15.
The half gradation voltage-generating portion 132 contains a plurality of resistive elements Ra, Rb, Rc, and Rd connected in series. The nodes Ta, Tb, Tc and Td are respectively connected to one terminal of both terminals of the resistive elements Ra, Rb, Rc and Rd. The nodes Tb, Tc, Td, and Te are respectively connected to the other terminals of the resistive elements Ra, Rb, Rc, and Rd.
The second switching portion 133 contains a plurality of switches Sa, Sb, Sc, Sd, and Se as the MOS transistor. The nodes Ta, Tb, Tc, Td and Te are respectively connected to the one ends of the switches Sa, Sb, Sc, Sd and Se. The buffer amplifier 126 is connected to the other ends of the plurality of switches Sa, Sb, Sc, Sd, and Se through a node Tout.
Herein, the above Z is set to 64, and the Z-pieces output gradation voltages are expressed as the output gradation voltages V00′ to V63′.
The gradation voltage control portion 130 performs a control shown in FIG. 4 to the first switching portion 131 and the second switching portion 133 so as to select the output gradation voltage in response to the display data Dj among the output gradation voltages V00′ to V63′.
For example, when the output gradation voltage in response to the display data Dj is V00′, the gradation voltage control portion 130 outputs a control signal to the switches S00, S01 and Sa as shown in FIG. 4.
At this time, the switch S00 is turned on in response to the control signal, and selects the gradation voltage applied to the node T0. The gradation voltage selected by the switch S00 is applied to the node Ta.
The switch S01 is turned on in response to the control signal, and selects the gradation voltage applied to the node T1. The gradation voltage selected by the switch S01 is applied to the node Te.
The half gradation voltage generating portion 132 voltage-divides the gradation voltage between the gradation voltage applied to the node Ta and the gradation voltage applied to the node Te into four equal parts, and generates three half gradation voltages. The three half gradation voltages are respectively applied to the nodes Tb, Tc and Td.
The switch Sa is turned on in response to the control signal, and outputs the gradation voltage applied to the node Ta as the output gradation voltage V00′. The output gradation voltage V00′ is applied to the node Tout, and is supplied to the buffer amplifier 126.
When the output gradation voltage in response to the display data Dj is V01′, the gradation voltage control portion 130 outputs the control signal to the switches S00, S01 and Sb as shown in FIG. 4.
At this time, the switch S00 is turned on in response to the control signal, and selects the gradation voltage applied to the node T0. The gradation voltage selected by the switch S00 is applied to the node Ta.
The switch S01 is turned on in response to the control signal, and selects the gradation voltage applied to the node T1. The gradation voltage selected by the switch S01 is applied to the node Te.
The half gradation voltage generating portion 132 voltage-divides the gradation voltage between the gradation voltage applied to the node Ta and the gradation voltage applied to the node Te into four equal parts, and generates the three half gradation voltages. The three half gradation voltages are respectively applied to the nodes Tb, Tc and Td.
The switch Sb is turned on in response to the control signal, and outputs the gradation voltage applied to the node Tb as the output gradation voltage V01′. The output gradation voltage V01′ is applied to the node Tout, and is supplied to the buffer amplifier 126.
However, the half gradation voltage generating portion 132 (resistive elements Ra, Rb, Rc and Rd) is arranged in parallel with series resistance voltage dividing circuit 127 (resistive elements R0 to R15). Therefore, there are problems in that the voltage levels of the output gradation voltages V00′ to V63′ are fluctuated by the error of a current flowing in the half gradation voltage generating portion 132. Thus, although the resistance values of the resistive elements R0 to R15 of the series resistance voltage dividing circuit 127 are usually tens of ohms to hundreds of ohms, the required resistance values of the resistive elements Ra, Rb, Rc and Rd of the half gradation voltage generating portion 132 are several mega ohms or more (for example, 1 mega ohm).
The number of outputs of the source driver circuit (source driver circuits 103-1 to 103-n) is several hundreds or more due to increasing resolution of the display portion 101 in recent years. That is, the above n is a value of several hundreds or more. When the source driver circuits 103-1 to 103-n select the same output gradation voltage simultaneously, an extremely high value of several mega ohms or more is required as the resistance values of the resistive elements Ra, Rb, R and, Rd of the half gradation voltage generating portion 132 so as to suppress the error of the current flowing in the half gradation voltage generating portion 132.
The size of the resistive element also becomes larger as the resistance value becomes higher. When the resistance values of the resistive elements Ra, Rb, Rc and Rd of the half gradation voltage generating portion 132 are several mega ohms or more, the circuit scale of the gradation voltage selecting circuit 125 becomes larger. The circuit scales of the source driver circuits 103-1 to 103-n, and the circuit scale of the liquid crystal drive circuit including the source driver circuits 103-1 to 103-n becomes larger as the circuit scale of the gradation voltage selecting circuit 125 becomes larger. Thus, the chip size of the chip on which the liquid crystal drive circuit is mounted is increased as the circuit scale becomes larger. As described above, the thin liquid crystal display device is required, and the chip size is preferably small.
Above-described gradation voltage selecting circuit 125 is obtained by simplifying the gradation voltage selecting circuit described in Japanese Laid Open Patent Application H09-198012A (1997). Japanese Laid Open Patent Application H09-198012A (1997) is also disclosed another gradation voltage selecting circuit of which the half gradation voltage generating portion 132 is changed into capacitors from the resistive elements. Even in this case, an extremely high value is required as the capacitance value of the capacitor because of the problems of the leak current of the capacitor itself and feed-through of the capacitor. The size of the capacitor also becomes larger as the capacitance value becomes higher. Even in this case, the circuit scale becomes larger, and causes the increase of the chip.